In recent ultra-LSI devices, it is necessary to integrate millions or more of elements on a chip of several mm square and therefore it is essential to miniaturize and multilayer each element. Particularly, in order to increase the device operating speed, it becomes an important subject to reduce the interconnection resistance and the interlayer capacitance.
For reducing the interconnection resistance and the interlayer capacitance, a method is employed that uses copper as an interconnection material and uses as an interlayer insulating film a film having a permittivity lower than that of a silicon oxide film. Further, the dual-damascene method is employed for reducing manufacturing processes and improving reliability of Cu interconnections. In the dual-damascene method, since a copper embedding process and a copper CMP (Chemical Mechanical Polishing) process can be omitted as compared with the single-damascene method, the manufacturing processes are largely shortened.
There is a prior art technique, called a via-first process, for forming a dual-damascene interconnection structure, which will be described hereinbelow.
First, as shown in FIG. 1A, a cap film 2 is formed on an upper surface of a lower interconnection structure 1. A via interlayer film 3 is formed on an upper surface of the cap film 2. As will be described later, the cap film 2 serves as an etching stopper in etching the via interlayer film 3. A stopper film 4 is formed on an upper surface of the via interlayer film 3. Further, a trench interlayer film 5 is formed on an upper surface of the stopper film 4. As will be described later, the stopper film 4 serves as an etching stopper in etching the trench interlayer film 5. Further, a hard mask 6 is formed on an upper surface of the trench interlayer film 5. As will be described later, the hard mask 6 serves as a cap film to prevent the trench interlayer film 5 from directly contacting a plasma. Subsequently, an antireflection film 7 and a photoresist 8 are formed on an upper surface of the hard mask 6. Further, the photoresist 8 is formed with a connection-hole-opening resist pattern 8a using the photolithography technique.
Subsequently, as shown in FIG. 1B, using the photoresist 8 formed with the connection-hole-opening resist pattern 8a as a mask, the antireflection film 7, the hard mask 6, the trench interlayer film 5, the stopper film 4, and the via interlayer film 3 are etched in order, thereby forming a connection-hole opening 3a. In this event, the etching of the via interlayer film 3 stops at the cap film 2.
After removal of the photoresist 8 and the antireflection film 7 as shown in FIG. 1C, an antireflection film 9 and a photoresist 10 are formed on the upper surface of the hard mask 6 as shown in FIG. 1D. The antireflection film 9 serves to protect the cap film 2 exposed at the bottom of the connection-hole opening 3a. Further, the photoresist 10 is formed with interconnection-trench resist patterns 10a and 10b using the photolithography technique.
Subsequently, as shown in FIG. 1E, the antireflection film 9, the hard mask 6, and the trench interlayer film 5 under the trenches of the resist pattern 10a are etched in order, thereby forming interconnection trench patterns 5a and 5b. The cap film 2 at the bottom of the connection-hole opening 3a is protected from an etching plasma by the antireflection film 9. After resist ashing (FIG. 1F), the cap film 2 exposed at the bottom of the connection-hole opening 3a is removed, thereby forming a dual-damascene structure.
Subsequently, as shown in FIG. 1G, copper is embedded in the connection-hole opening 3a and the interconnection trenches 5a and 5b, thereby forming Cu interconnections 11.
If the conventional dual-damascene formation process as described above is carried out using an exposure pattern (pattern transfer mask) produced for single damascene, there may arise a serious problem in the case where a plurality of interconnections (an interconnection interval given by d) are formed at a fine pitch and a via is connected to at least one of the interconnections. If exposure of a via and exposure of an upper-layer interconnection are misaligned with each other by Δx as shown in FIG. 1D, the distance between the misaligned via and an interconnection adjacent thereto becomes (d−Δx) as shown in FIG. 1G and thus is shortened by Δx. Since the distance between the adjacent interconnections is shortened, there is concern about a reduction in insulating properties of the interconnections and a possibility of a short circuit therebetween.
In the conventional technique as described above, the dual-damascene method is used for reducing the interconnection processes and improving the reliability of Cu interconnections.
However, in the foregoing dual-damascene formation method, there has been a problem of a reduction in insulating properties of a fine-pitch interconnection pattern with a via.
In order to solve this problem, a new process is required that can suppress a reduction in insulating properties of a fine-pitch interconnection pattern with a via even if a misalignment occurs.